Recently, crossbar array based in-memory accelerators have been gaining interest due to their high throughput and energy efficiency. While software and compiler support for the in-memory accelerators has also been introduced, they are currently limited to the case where all weights are assumed to be on-chip. This limitation becomes apparent with the significantly increasing network sizes compared to the in-memory footprint. Weight replacement schemes are essential to address this issue. We propose COMPASS, a compiler framework for resource-constrained crossbar-based processing-in-memory (PIM) deep neural network (DNN) accelerators. COMPASS is specially targeted for networks that exceed the capacity of PIM crossbar arrays, necessitating access to external memories. We propose an algorithm to determine the optimal partitioning that divides the layers so that each partition can be accelerated on chip. Our scheme takes into account the data dependence between layers, core utilization, and the number of write instructions to minimize latency, memory accesses, and improve energy efficiency. Simulation results demonstrate that COMPASS can accommodate much more networks using a minimal memory footprint, while improving throughput by 1.78X and providing 1.28X savings in energy-delay product (EDP) over baseline partitioning methods.

In this role, you will be part of the AI compiler team and the part of the bigger industry-leading PyTorch ML Framework team. The AI Compiler team has been developing a comprehensive AI Compiler strategy that delivers a highly flexible platform to explore new DL/ML model architectures, combined with auto-tuned high performance for production environments across a wide range of hardware architectures. You will be developing AI compiler frameworks to accelerate machine learning workloads on the next generation of AI hardware. You will work closely with AI researchers to analyze deep learning models and how to lower them efficiently on AI platforms. You will also partner with hardware design teams to develop compiler optimizations for high performance.